DANIEL ÁNGEL CHAVER MARTÍNEZ

  Associate Professor
Department of Computer Architecture and System Engineering
Universidad Complutense de Madrid
          

 

 

Tutorial at ISCA-18:

Teaching Computer Architecture using MIPSfpga v2.0

 

 

My Research
 
  • My main interests: Cache Hierarchy, Non-Volatile Memory (PCM, Race-Track), Asymmetric MultiProcessors (AMPs).
Selected publications/patents
 
  • "Fetching Instructions in an Instruction Fetch Unit" (United States Patent Application 20170364357) - "Method of fetching instructions in an instruction fetch unit" (Great Britain Application GB201610541D0)
  • "Reuse Detector: Improving the Management of STT-RAM SLLCs" (ComputerJournal-17)
  • "Practical experiences based on MIPSfpga" (WCAE-17 held in conjunction with ISCA-17)
  • "Towards completely fair scheduling on asymmetric single-ISA multicore processors" (JPDC-17)
  • "MIPSfpga: using a commercial MIPS soft-core in computer architecture education" (IET_CDS-17)
  • "OpenIRS-UCM: an Integral Solution for Interactive Response Systems" (JournalEngineeringEducation-16)
  • "Write-aware replacement policies for PCM-based systems" (ComputerJournal-15)
  • "An OS-Oriented Performance Monitoring Tool for Multicore Systems" (Europar-15)
  • "ACFS: A Completely Fair Scheduler for Asymmetric Single-ISA Multicore Systems" (SAC-15)
  • "Online Evaluation Methodology of Laboratory Sessions in Computer Science Degrees" (IEEE-RITA-14)
  • "Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems" (EuroPar-ROME-14)
  • "Improving Pelifo Cache Replacement Policy: Hardware Reduction and Thread-Aware Extension" (JCSC-14)
  • "Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling" (Sigmetrics-13)
  • "Reducing Writes in PCM Environments by Using Efficient Cache Replacement Policies" (DATE-13)
  • "A hybrid timing-address oriented LSQ filtering for an x86 architecture" (IET CDT-11)
  • "L1 Data Cache Power Reduction using a Forwarding Predictor" (PATMOS-10)
  • "Replacing Associative Load Queues: A Timing Centric Approach" (IEEE Transactions on Computers-09)
  • "DMDC: Delayed Memory Dependence Checking through Age-Based Filtering" (MICRO-06)
  • "Substituting Associative Load Queue with Simple Hash Table in OoO Microprocessors" (ISLPED-06)
  • "LSQ Management: an Energy Efficient Design based on a State Filtering Mechanism" (ICCD-05)
  • "Energy-Aware Fetch Mechanism: Trace Cache and BTB Customization" (ISLPED-05)
  • "Customizing the Branch Predictor to Reduce Complexity and Energy Consumption" (IEEE Micro-03)
  • "Branch Prediction On Demand: An Energy-Efficient Solution" (ISLPED-03)
  • "Vectorization of the 2D Wavelet Lifting transform using SIMD extensions" (PDIVM - 03 held in conjunction with IPDPS-03)
  • "2-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation" (HIPC-02)
  • "Parallel Wavelet Transform for Large Scale Image Processing" (IPDPS-02)

 

My Teaching (2017-18)

 
  • IoT Node Architecture (Master IoT)
  • Computer Organization (Degree in Computer Science / Electrical Engineering)
  • Integrated Systems Architecture (Degree in Telecommunications Engineering)
   

 

  

Contact Information
  dani02ucm.es

  Office: 236.0 (Facultad CC. Físicas)
  Phone: +34 91 394 4105
 

  Postal address:
    Departamento de Arquitectura de Computadores y Automática
   Facultad CC. Físicas
   Ciudad Universitaria, s/n
   Universidad Complutense de Madrid
   28040, Madrid, Spain

 

 

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