Tutorial at ISCA 2018



The MIPSfpga project, developed in a collaboration between MIPS LLC, Digilent Inc. (a National Instruments Company), Xilinx and several universities (UNLV, HMC and UCM), constitutes a comprehensive resource for education on computer architecture, system-on-chip (SoC) design and hardware-software co-design. It not only provides open access to the MIPS microAptiv UP soft-core processor, a member of the same family found in many embedded devices such as the PIC32MZ microcontroller from Microchip, but it also includes a large set of teaching materials and software tools.

The MIPSfpga 2.0 package presented at this workshop shows how to, among other things, set up the MIPS soft-core processor on an FPGA; run and debug programs on the core in simulation and in hardware; add new peripherals to the system by designing and implementing the hardware controller in Verilog or VHDL and the software controller in C or MIPS assembly; understand the use of interrupts and a direct memory access (DMA); understand the microarchitecture and extend it to support new features, such as new instructions; use the performance counters; analyze the cache controller and experiment with different cache configurations, optimization techniques and content management policies; use the CorExtend interface available in MIPS processors for adding new instructions, for example ones that use a floating point unit (FPU) or a digital signal processor (DSP); and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

The tutorial is open to academic faculty members. It includes short talks, demonstrations, and hands-on activities. Basic knowledge of digital design, computer architecture and HDL design is required. After this training, attendees will be proficient in using MIPSfpga and be aware of its potential to revolutionize their teaching.


HW/SW Requirements:


- You will need to bring your own laptop. Windows and Linux operating systems are both supported.

- At the tutorial, we will lend you the remaining hardware required for the guided and hands-on activities: Nexys4 DDR, BusBlaster, Pmod ALS.


- You will need to pre-install some programs. We will provide detailed instructions several weeks before the tutorial.



8-8:30: Introduction

8:30-10: MIPSfpga Overview (MIPSfpga GSG and Part 1 of MIPSfpga Labs): Setting up the microAptiv core on an FPGA. Running and debugging programs on the core, both in simulation and in hardware.

10-10:30: Mid-morning Break

10:30-12:30: I/O with MIPSfpga (Part 2 of MIPSfpga Labs): Expanding MIPSfpga to add new peripherals (polling and interrupts). Performance evaluation and measurement of major core components.

12:30-13:30: Lunch

13:30-15:30: The Core (Part 3 of MIPSfpga Labs): Delving into the core to trace instructions through the pipeline and examine pipeline hazards. Expanding the core to support user-defined instructions, both using the CorExtend interface and by modifying the core hardware itself.

15:30-16: Mid-afternoon Break

16-17:30: The Memory System (Part 4 of MIPSfpga Labs): Implementing and experimenting with different memory hierarchies, cache sizes, associativities and content management policies.

17:30-18: Introduction to MIPSfpga SoC


Organized by:

- Daniel Chaver, University Complutense of Madrid

- Sarah Harris, University of Nevada Las Vegas

- Larissa Swanland & Robert Owen, Digilent

- Jay Ng, MIPS