Curriculum Vitae

November 2010

José Ignacio HIDALGO PÉREZ

Departamento de Arquitectura de Computadores y Automática

Facultad de Informática

Universidad Complutense de Madrid, 28040 Madrid, España

Teléfono: +34-91-39447537, Fax: +34-91-3947527

E-Mail: hidalgo@dacya.ucm.es,

Web:http://www.dacya.ucm.es/hidalgo

BOOKS

1.                  J.L. Risco-Martín, D. Atienza, J.I. Hidalgo, J.Lanchares. Parallel and Distributed Optimization of Dynamic Data Structures for Multimedia Embedded Systems. Chapter from Parallel and Distributed Computational Intelligence        Series: Studies in Computational Intelligence , Vol. 269 Francisco Fernández de Vega; Erick Cantú-Paz, (Eds.) 2010, VI,  pp 263-290, Hardcover ISBN: 978-3-642-10674-3

2.                  A. Cuesta, J.I. Hidalgo, J. Lanchares, J.L. Risco. Problemas de Fundamentos y Estructura de Computadores. Pearson Educación. ISBN 9788483225912, 568 páginas

3.                  J.I. Hidalgo (editor). Anales de Ingeniería Técnica en Informática de Sistemas. Volumen II. Editorial Felipe II Libros. Aranjuez Madrid. Abril 2009. (ISBN: 978-84-935511-2-4)  

4.                  J.I. Hidalgo (editor). Anales de Ingeniería Técnica en Informática de Sistemas. Volumen I. Editorial Felipe II Libros. Aranjuez Madrid. Mayo 2007. (ISBN: 978-84-935511-2-4)  

5.                  C. Córdoba, J.C. Pedraz, C. Tenllado, J.I. Hidalgo.  Implementación de un Algoritmo Genético Paralelo sobre Hardware Gráfico de última Generación. 2005. (ISBN: 84-689-7987-2)  

6.                  F. Fernández, J.I. Hidalgo, J. Lanchares, J.M. Sánchez. Chapter from Evolvable Machines Theory & Practice. Series: Studies in Fuzziness and Soft Computing , Vol.  161 Nedjah, Nadia; de Macedo Mourelle, Luiza (Eds.) 2005, XXVI, pp 151-177., Hardcover  (ISBN: 3-540-22905-1).  

7.                  E. Alba, F. Fernández, J.A. Gómez, F. Herrera, J.I. Hidalgo,  J. Lanchares, J.J. Merelo, J.M. Sánchez. Editors. Actas del Primer Congreso Español de Algoritmos Evolutivos y Bioinspirados (AEB´02), Mérida. February 2002. (ISBN: 84-607-3913-9).

8.                  J.I. Hidalgo. Técnicas de Partición y Ubicación para sistemas Multi-FPGA basadas en Algoritmos genéticos. PhD Tesis. Complutense University of Madrid. December 2001. (ISBN: 84-689-7988-0).  

9.                  N. Joglar, R. Sánchez, A. Díaz, D. Martín, J.M. Colmenar, I. Martínez, A. Cuesta,J.L. Risco y J.I. Hidalgo. Evaluación online en educación secundaria y universitaria. Anales de Ingeniería Técnica en Informática de Sistemas. Volumen I. PÁG. 13-24. Editorial Felipe II Libros. J.I. Hidalgo (editor). Aranjuez Madrid. Mayo 2007. ISBN: 978-84-935511-2-4.  

10.             J.M. Colmenar, J.I. Hidalgo, O. Garnica, J. Lanchares. Sistemas asíncronos. Anales de Ingeniería Técnica en Informática de Sistemas. Volumen I. PÁG. 83-92. Editorial Felipe II Libros. J.I. Hidalgo (editor). Aranjuez Madrid. Mayo 2007. ISBN: 978-84-935511-2-4.  

11.             D. Bodas, P. Fernández, F. Soltero, J.I. Hidalgo. Aplicación de los algoritmos genéticos a la economía. Anales de Ingeniería Técnica en Informática de Sistemas. Volumen I. Editorial Felipe II Libros. J.I. Hidalgo (editor). Aranjuez Madrid. Mayo 2007. ISBN: 978-84-935511-2-4.  

12.             J.I. Hidalgo. Prólogo del libro Exámenes finales: La solución del profesor. Varios Autores. Editorial Felipe II libros, Aranjuez, 2008. ISBN: 978-84-935511-4-8.  

 

INTERNATIONAL JOURNALS

13.              J. I. Hidalgo. F. Fernández, J. Lanchares, E. Cantú-Paz, A. Zomaya. Special Issue on Parallel Architectures and Bio-inspired Algorithm. Guest editorial.  Parallel Computing Journal. Elsevier. Vol 36, issues 10-11, pp 553-554. ISSN: 0167-8191

14.             J. M. Colmenar , O. Garnica , J. Lanchares , J. I. Hidalgo. Characterizing Asynchronous Variable Latencies through Probability Distribution Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 483-497 (2009); ISSN:0141-9331

15.             Nuria Joglar, Diego Martín, J. Manuel Colmenar, Iván Martínez, J. Ignacio Hidalgo, (2010) "iTest: online assessment and self-assessment in mathematics", Interactive Technology and Smart Education, Vol. 7 Iss: 3, pp.154 - 167 J

16.             J. I. Hidalgo. Special Issue on Parallel Architectures and Bio-inspired Algorithm. Guest editor.  International Journal of High Performance Systems Architecture. Volume 1, No. 4: 2008. ISSN (Print): 1751-6528, ISSN (Online): 1751-6536.  

17.             J. L. Risco-Martín, O. Garnica, J. Lanchares, J. I. Hidalgo and D. Atienza. Particle swarm optimisation of memory usage in embedded systems. International Journal of High Performance Systems Architecture. Volume 1, No. 4: 209-219, 2008. ISSN (Print): 1751-6528, ISSN (Online): 1751-6536.  

18.             C. Baloukas, J.L. Risco-Martín, D. Atienza, C. Poucet, L. Papadopoulos, S. Mamagkakis, D. Soudris, J.I. Hidalgo, F. Catthoor, J. Lanchares: Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems. Journal of Systems and Software (JSS) 82(4):590-602 (2009)  

19.             J. L. Risco-Martín, D. Atienza, J.I. Hidalgo, J. Lanchares. A Parallel Evolutionary Algorithm to Optimize Dynamic Data Types in Embedded Systems. Soft Computing - A Fusion of Foundations, Methodologies and Applications (Magazine) (2008) 12:1157–1167.  

20.             G. Miñana, J.I. Hidalgo, O. Garnica, J. Lanchares, J.M. Colmenar. S. López. Reducing Power of Functional Units in High Performance Processors by checking instructions codes and resizing adders. IEE-proceedings Computers and Digital Techniques. Institution of Engineering and Technology (IET). Vol 1 (2) pp 113-119. ISSN: (1350-2387)  

21.             C. Sequeira, F. Sanchez-Quesada, M. Sancho, J.I. Hidalgo and T. Ortiz. A Genetic Algorithm Approach for Localization of Deep Sources in MEG. Physica Scripta. Vol. T118, 140–142, 2005. (ISSN: 0031-8949).  

22.             G. Miñana, J.I. Hidalgo, O. Garnica, D. Gil. Asynchronous circuit implementation using FPGAs. IADAT Journal of Advanced Technology on Automation, Control and Instrumentation, IJAT-aci, Vol.1(1), 16-18. September 2005. (ISSN: 1885-6403).  

23.             F. Fernández, J.I. Hidalgo, J. Lanchares, J.M. Sánchez. A Methodology for Reconfigurable Hardware Design based upon Evolutionary Computation. Microprocessors and Microsystems, Elsevier Science, September 2004. Clave: A; Volumen: 28, issue 7; Paginas 363-371; (ISSN: 0141-9331).  

24.             R. Baraglia, J.I. Hidalgo, R. Perego. A Hybrid Heuristic for the Travelling Salesman Problem. IEEE Transactions on Evolutionary Computation, Vol.: 5, Nº6, pp 613-622. December 2001. (ISSN: 1089-778X).  

25.             J. Lanchares, J.I. Hidalgo, J.M. Sánchez. A method for multiple-level systems based on the SA algorithm. Microelectronics Journal. Elsevier Science. Vol. 28, Nº 5, pp 551-560, June 1997. (ISSN: 0026-2692).  

26.             J. Lanchares, J.I. Hidalgo, J.M. Sánchez. Boolean networks decomposition using genetic algorithms. Microelectronics Journal. Elsevier Science. Vol. 28, Nº. 2, pp 143-150, February 1997. (ISSN: 0026-2692).  

INTERNATIONAL CONFERENCES

2010

27.             Josefa Díaz Álvarez, Francisco Fernández de Vega, José Ignacio Hidalgo, Oscar Garnica “PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches”. Proceedings of the International Conference on Evolutionary Computation, pp 275-280. Valencia Noviembre 2010, Lugar de Publicación: Portugal. ISBN: 978-989-8425-31-7. .

28.             David Millán-Ruiz, José Ignacio Hidalgo , Josefa Díaz Álvarez.  COMPARISON OF METAHEURISTICS FOR MULTI-SKILL CALL CENTRES.  Proceedings of the International Conference on Evolutionary Computation, pp 352-358. Valencia Noviembre 2010, Lugar de Publicación: Portugal. ISBN: 978-989-8425-31-7.

29.             J. Ignacio Hidalgo and Juan Lanchares. Let them be the ones to invent? Spanish Pioneers of Computer and Telecommunications (paper nº 60), The Second Region 8 IEEE Conference on the History of Telecommunications Madrid, Spain 3-5 November 2010. IEEE Press.

30.             D. Millán-Ruiz, J.I. Hidalgo. Proceedings of the tird international workshop on parallel architectures and bio-inspired algorithms (WPABA 2010). Viena (Austria) 12 September 2010. Editors J. M. Colmenar and D. Lombraña. Pp , Universidad Complutense de Madrid, ISBN:.

31.              J. M. Colmenar, O. Garnica, J. Lanchares and J.I. Hidalgo. Simulating a LAGS Processor to Consider Variable Latency on L1 D-Cache. Proceedings of Summer Computer Simulation Conference 2010 (SCSC'10). Editors: Wainer, G., A. Tolk, P. Kropf, and M. Itmi. Volume 1, pp 56-63, July 2010 Ottawa, Canadá. Publisher Society for Modeling and Simulation International. ISBN: 978-1-61738-702-9.

32.             J.L. Risco, J.M. Colmenar, D.Atienza, J.I. Hidalgo. Simulation of High-Performance Memory Allocators. Proceedings of the 13th Euromicro Conference on Digital System Design (DSD 2010), Lille (France), September 1-3, 2010. vol. 1, num. 1, 2010, p. 275-282. New York: IEEE Press, 2010. ISBN: 978-0-7695-4171-6.

33.             , S. López, O. Garnica, D.H. Albonesi, S. Dropsho, J. Lanchares, and J.I. Hidalgo. Adaptive Cache Memories for SMT Processors. Proceedings of the 13th Euromicro Conference on Digital System Design (DSD 2010), Lille (France), September 1-3, 2010. vol. 1, num. 1, 2010, p. 331-338. New York: IEEE Press, 2010. ISBN: 978-0-7695-4171-6.

34.             Cuesta, D., Ayala, J.I., Hidalgo, J., Poncino, M., Acquaviva, A., and Macii, E. 2010. Thermal-aware floorplanning exploration for 3D multi-core architectures. In Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI (Providence, Rhode Island, USA, May 16 - 18, 2010). GLSVLSI '10. ACM, New York, NY, 99-102. DOI= http://doi.acm.org/10.1145/1785481.1785505  

35.             Cuesta, D.; Ayala, J.L.; Hidalgo, J.I.; Atienza, D.; Acquaviva, A.; Macii, E.; , "Adaptive Task Migration Policies for Thermal Control in MPSoCs," VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on VLSI, vol., no., pp.110-115, 5-7 July 2010 doi: 10.1109/ISVLSI.2010.39

36.             Cuesta-Infante, Alfredo; Santana, Roberto; Hidalgo, J. Ignacio; Bielza, Concha; Larranaga, Pedro; , "Bivariate empirical and n-variate Archimedean copulas in estimation of distribution algorithms," Evolutionary Computation (CEC), 2010 IEEE Congress on , vol., no., pp.1-8, 18-23 July 2010.

37.             Colmenar, J. M., Risco-Martín, J. L., Atienza, D., Garnica, O., Hidalgo, J. I., and Lanchares, J. 2010. Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. In Proceedings of the 12th Annual Conference on Genetic and Evolutionary Computation (Portland, Oregon, USA, July 07 - 11, 2010). GECCO '10. ACM, New York, NY, 1227-1234. DOI= http://doi.acm.org/10.1145/1830483.1830705

38.             D. Millán-Ruiz, J.I. Hidalgo, A Memetic Algorithm for Workforce Distribution in Dynamic Multi-Skil Call Centres. Proceedings of the 10th European Conference on Evolutionary Computation in Combinatorial Optimisation (EVOCOP 2010), p. 178-189, Istanbul, Turkey, April 7-9, Lecture Notes in Computer Science 6022- Springer Berlin / Heidelberg, doi: 10.1007/978-3-642-12139-5_16

39.             Millán-Ruiz, D.; Pacheco, J.; Hidalgo, I. y Vélez, J.L.: Forecasting in a Multi-skill Call Centre. To appear in the 10th International Conference on Artificial Intelligence and Soft Computing (ICAISC 2010), Zakopane, Poland, June 13-17, 2010. Lecture Notes in Computer Science, 2010, Volume 6114, Artifical Intelligence and Soft Computing, Pages 582-589.

2009

 

40.             G. Miñana, A. Acquaviva, D. Atienza, G. deMicheli, L. Benini, J.I. Hidalgo. Operating System Based Simulation Framework for Validation of Power Management Policies in Embedded Systems. Proceedings of the 4th International Conference on Intelligent Systems and Knowledge Engineering (ISKE 2009). November 27-28, 2009, Hasselt Belgium. Pp 305-310. ISBN:   978-981-4295-05-5. World Scientific.

41.             PACT 2009 María José . Proceedings of  The second international workshop on parallel architectures and bio-inspired algorithms (WPABA 2009). Editors José L. Risco-Martín and Oscar Garnica. Pp , Universidad Complutense de Madrid, ISBN: 978-84-692-3675-8.

42.             Risco-Martín, J. L., Hidalgo, J. I., Atienza, D., Lanchares, J., and Garnica, O. 2009. Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. In Proceedings of the 11th Annual Conference on Genetic and Evolutionary Computation (Montreal, Québec, Canada, July 08 - 12, 2009). GECCO '09. ACM, New York, NY, 1601-1608. DOI= http://doi.acm.org/10.1145/1569901.1570115

43.             Risco-Martín, J. L., Atienza, D., Gonzalo, R., and Hidalgo, J. I. 2009. Optimization of dynamic memory managers for embedded systems using grammatical evolution. In Proceedings of the 11th Annual Conference on Genetic and Evolutionary Computation (Montreal, Québec, Canada, July 08 - 12, 2009). GECCO '09. ACM, New York, NY, 1609-1616. DOI= http://doi.acm.org/10.1145/1569901.1570116.

44.             Bodas-Sagi, D. J., Fernández, P., Hidalgo, J. I., Soltero, F. J., and Risco-Martín, J. L. 2009. Multiobjective optimization of technical market indicators. In Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers (Montreal, Québec, Canada, July 08 - 12, 2009). GECCO '09. ACM, New York, NY, 1999-2004. DOI= http://doi.acm.org/10.1145/1570256.1570266

45.             Díaz, J., Hidalgo, J. I., Fernández, F., Garnica, O., and López, S. 2009. Improving SMT performance: an application of genetic algorithms to configure resizable caches. In Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers (Montreal, Québec, Canada, July 08 - 12, 2009). GECCO '09. ACM, New York, NY, 2029-2034. DOI= http://doi.acm.org/10.1145/1570256.1570271.

2008

 

46.             Risco-Martín, J. L., Atienza, D., Hidalgo, J. I., and Lanchares, J. 2008. Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. In Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (September 03 - 05, 2008). IEEE Computer Society, Washington, DC, 455-463. DOI= http://dx.doi.org/10.1109/DSD.2008.118

47.             J.I. Hidalgo, F. Fernández, J. Lanchares. Welcome Letter. Proceedings of the 1st Workshop on Parallel Architectures and Bioinspired Algorithms (In conjunction with PACT 2008). J. Lanchares, F. Fernández, J.L. Risco-Martín, O. Garnica (Editors). Pp 1-4.

48.             J. Lanchares,  J.I. Hidalgo, F. Fernández. A Review of Bioinspired CAD Tools for Hardware Design. Proceedings of the 1st Workshop on Parallel Architectures and Bioinspired Algorithms (In conjunction with PACT 2008). J. Lanchares, F. Fernández, J.L. Risco-Martín, O. Garnica (Editors).

49.             O. Garnica, J.L. Risco-Martín, J.I. Hidalgo, J. Lanchares. Speeding-up Resolution of Deceptive Problems by a Parallel GPU-CPU Architecture. Proceedings of the 1st Workshop on Parallel Architectures and Bioinspired Algorithms (In conjunction with PACT 2008). J. Lanchares, F. Fernández, J.L. Risco-Martín, O. Garnica (Editors).

50.              J.L. Risco-Martín, J.I. Hidalgo, O. Garnica, D. Atienza, J. Lanchares. Particle Swarm Optimization of Memory usage in Embedded Systems Proceedings of the 1st Workshop on Parallel Architectures and Bioinspired Algorithms (In conjunction with PACT 2008). J. Lanchares, F. Fernández, J.L. Risco-Martín, O. Garnica (Editors).

51.             J.M. Colmenar, N. Morón, O. Garnica, J. Lanchares, J.I. Hidalgo. Modelling asynchronous systems using probability distribution functions. 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (Congress) 2008. pp.3-11, 13-15 Feb. 2008. doi: 10.1109/PDP.2008.34

52.             Risco-Martín, J. L., Mittal, S., Atienza, D., Hidalgo, J. I., and Lanchares, J. 2008. Optimization of dynamic data types in embedded systems using DEVS/SOA-based modeling and simulation. In Proceedings of the 3rd international Conference on Scalable information Systems (Vico Equense, Italy, June 04 - 06, 2008). ICST (Institute for Computer Sciences Social-Informatics and Telecommunications Engineering), ICST, Brussels, Belgium, 1-11.

53.             Risco-Martín, J. L., Atienza, D., Hidalgo, J. I., and Lanchares, J. 2008. Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. In Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (September 03 - 05, 2008). DSD. IEEE Computer Society, Washington, DC, 455-463. DOI= http://dx.doi.org/10.1109/DSD.2008.118

54.             Fernández-Blanco, P., Bodas-Sagi, D. J., Soltero, F. J., and Hidalgo, J. I. 2008. Technical market indicators optimization using evolutionary algorithms. In Proceedings of the 2008 GECCO Conference Companion on Genetic and Evolutionary Computation (Atlanta, GA, USA, July 12 - 16, 2008). M. Keijzer, Ed. GECCO '08. ACM, New York, NY, 1851-1858. DOI= http://doi.acm.org/10.1145/1388969.

55.             Hidalgo, J. I., Risco-Martín, J. L., Atienza, D., and Lanchares, J. 2008. Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. In Proceedings of the 10th Annual Conference on Genetic and Evolutionary Computation (Atlanta, GA, USA, July 12 - 16, 2008). M. Keijzer, Ed. GECCO '08. ACM, New York, NY, 1515-1522. DOI= http://doi.acm.org/10.1145/1389095.1389388

56.             Risco-Martín, J. L., Hidalgo, J. I., Lanchares, J., and Garnica, O. 2008. Solving discrete deceptive problems with EMMRS. In Proceedings of the 10th Annual Conference on Genetic and Evolutionary Computation (Atlanta, GA, USA, July 12 - 16, 2008). M. Keijzer, Ed. GECCO '08. ACM, New York, NY, 1139-1140. DOI= http://doi.acm.org/10.1145/1389095.1389317

2007

 

57.             N. Joglar, J.M. Colmenar, D. Martín, R. Sánchez, J. L. Risco, J.I. Hidalgo, A. Díaz, “iTest: a web application for learner-directed assessment in all levels, supporting mathematical formula and multimedia files”. IADIS-CELDA Conference. December 2007. Portugal.

58.             Hidalgo, J. I., de Vega, F. F., Lanchares, J., and Lombraña, D. 2007. Is the island model fault tolerant?. In Proceedings of the 9th Annual Conference on Genetic and Evolutionary Computation (London, England, July 07 - 11, 2007). GECCO '07. ACM, New York, NY, 1519-1519 begin_of_the_skype_highlighting              1519-1519      end_of_the_skype_highlighting. DOI= http://doi.acm.org/10.1145/1276958.1277248

59.             Hidalgo, J. I., Lanchares, J., Fernández de Vega, F., and Lombraña, D. 2007. Is the island model fault tolerant?. In Proceedings of the 2007 GECCO Conference Companion on Genetic and Evolutionary Computation (London, United Kingdom, July 07 - 11, 2007). GECCO '07. ACM, New York, NY, 2737-2744 begin_of_the_skype_highlighting  end_of_the_skype_highlighting. DOI= http://doi.acm.org/10.1145/1274000.1274085.

60.             R. González, B. Barán, J.I. Hidalgo. Multiobjective Optimization for the Circuit Partitioning Problem into Multiple Devices. Southern Programmable Logic 07. Designer´s Forum Workshop, pp 9-14. (ISBN: 84-611-4716-2).

61.             Atienza, D., Baloukas, C., Papadopoulos, L., Poucet, C., Mamagkakis, S., Hidalgo, J. I., Catthoor, F., Soudris, D., and Lanchares, J. 2007. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. In Proceedingsof the 10th international Workshop on Software &Amp; Compilers For Embedded Systems (Nice, France, April 20 - 20, 2007). H. Falk and P. Marwedel, Eds. SCOPES '07, vol. 235. ACM, New York, NY, 31-40. DOI= http://doi.acm.org/10.1145/1269843.1269849

2006

 

62.             J. M. Colmenar, O. Garnica, J. Lanchares, J.I. Hidalgo, G. Miñana. Sim-async: an Architectural Simulator for Asynchronous Processor Modelling using Distribution Functions. Proceedings of Europar 2006. Lecture Notes in Computer Science, Springer, Montpellier (France), September 2006. Clave: A, Volumen: 4128; Páginas: 495-505; (ISSN: 0302-9743).

63.             G. Miñana, J.I. Hidalgo, O. Garnica, J. Lanchares, J.M. Colmenar. S. López. A Technique to reduce Static and Dynamic Power of Functional Units in High-Performance Processors. Proceedings of 33th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS 06), Lecture Notes in Computer Science, Springer, Montpellier (France), September 2006. Clave: A, Volumen: 4148; Páginas: 514-523; (ISSN: 0302-9743)

64.             J. M. Colmenar, Oscar Garnica, Juan Lanchares, J.I. Hidalgo, and Guadalupe miñana. Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. Proceedings of 9th EUROMICRO Conference on Digital System Design (DSD'06). September 2006. pp. 423-432.

65.             G. Miñana, J.I. Hidalgo, O. Garnica, J. Lanchares, J.M. Colmenar. S. López. A Power-Aware Technique for Functional Units in High-Performance Processors. Proceedings of 9th EUROMICRO Conference on Digital System Design (DSD'06)   pp. 456-459

2005

66.             G. Miñana, O. Garnica, J.I. Hidalgo, J. Lanchares, J.M. Colmenar. Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. Proceedings of 32th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS 05), Lecture Notes in Computer Science, Springer, Leuven (Belgium), September 2005. Clave: A Volumen: 3728; Páginas: 40-48; (ISSN: 0302-9743)

67.             S. López, O. Garnica, J.I. Hidalgo, J. Lanchares, J. M. Colmenar, G. Miñana. Study of the communication channels in a GALS SMT Architecture. 2nd IADAT international Conference on Automation, Control and Instrumentation. 5-7 July 2005, Valencia (Spain). Páginas 36-40. (ISBN: 84-933971-8-0.)

68.             J.I. Hidalgo and F. Fernandez. Balancing the Computation Effort in Genetic Algorithms. 2005 IEEE Congress on Evolutionary Computation and Edinburgh (United Kigdom). Publication Date: 2-5 Sept. 2005 Volume: 2,  On page(s): 1645- 1652, ISBN: 0-7803-9363-5.

69.             D. Gil, G.Miñana, J.I. Hidalgo, O. Garnica. Adaptation and Automation of the FPGA Design Flow for asynchronous circuit implementation. IADAT internactional Conference on Automation, Control and Instrumentation. 2-4 February 2005, Bilbao (Spain). ISBN: 84-933971-2-1.

70.             G. Miñana, J.I. Hidalgo y J.Lanchares. Power-Aware Technique for Functional Unit in High-Performance Processors. International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005).

2004

71.             J. M. Colmenar, O. Garnica, S. López, J.I. Hidalgo, J. Lanchares, R. Hermida. Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. Proceedings. 12th Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2004. IEEE Press. La Coruña (Spain) February 2004. pp: 311-321, (ISBN: 0-7695-2083-9).

2003

 

72.             J.I. Hidalgo, F. Fernández, J. Lanchares, J. M. Sánchez-Pérez, R. Hermida, M. Tomassini, R. Baraglia, R. Perego, O. Garnica. Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. Proceedings of GECCO 2003 Lecture Notes in computer Science, Springer. Chicago (USA), July 2003. Clave: A Volumen: 2724; Páginas: 2109-2120; (ISSN:0302-9743)

73.             S. López, O. Garnica, J.I. Hidalgo, J. Lanchares, R. Hermida. Power-consumption reduction in asynchronous circuits using delay path unequalization. Proceedings of Thirteenth International Workshop on Power And Timing Modelling, Optimization and Simulation (PATMOS 03), Lecture Notes in Computer Science, Springer, Torino (Italy), September 2003. Clave: A; Volumen: 2799; Páginas:151-160; (ISSN: 0302-9743).

74.             Hidalgo, J.I.; Prieto, M.; Lanchares, J.; Baraglia, R.; Tirado, F.; Garnica, O.; , "Hybrid parallelization of a compact genetic algorithm," Parallel, Distributed and Network-Based Processing, 2003. Proceedings. Eleventh Euromicro Conference on , pp. 449- 455,5-7. Feb 2003. doi: 10.1109/EMPDP.2003.1183624.

75.             C. Sequeira, F. Sánchez-Quesada, M. Sancho, J.I. Hidalgo, T. Ortiz. A Genetic Algorithm Approach For Localization Of Deep Sources In Meg C, First International Conference on Applied Physics. APHYS 03, 13-18th October 2003, Badajoz (Spain).

2002

76.              J.I. Hidalgo, J. Lanchares, R. Hermida, A. Ibarra. A Genetic approach for Graph Partitioning. An Application to Multi-FPGA systems. 6th World Multiconference on Systemics, Cybernetics and Informatics. The 8th International Conference on Information System Analysis and Synthesis. Electronic Proceedings. 14 –18 July 2002, Orlando (USA).

77.             Hidalgo, J.I.; Lanchares, J.; Ibarra, A.; Hermida, R.; , "A hybrid evolutionary algorithm for Multi-FPGA systems design," Digital System Design, 2002. Proceedings. Euromicro Symposium on, pp. 60- 67, 2002 doi: 10.1109/DSD.2002.1115352.

78.             Ibarra, A.; Mendias, J.M.; Lanchares, J.; Hidalgo, J.I.; Hermida, R.; , "Optimization of equational specifications using genetic techniques," Digital System Design, 2002. Proceedings. Euromicro Symposium on , pp. 252- 258, 200 doi: 10.1109/DSD.2002.1115376

79.             A. Ibarra, J. Lanchares, J.M. Mendías, J.I. Hidalgo, R. Hermida. Transformation of Equational Specification by means of Genetic Programming. Genetic Programming, 5th European Conference, EuroGP 2002 Kinsale, Ireland, April 3–5, 2002 Proceedings. James A. Foster, Evelyne Lutton, Julian Miller, Conor Ryan and Andrea Tettamanzi Eds. Lecture Notes in Computer Science. Clave: A; Volumen: 2278, pp 248-257. Springer. Kinsale, Ireland, April 2002. (ISSN 0302-9743)

2001

80.             R. Baraglia, J.I. Hidalgo, R. Perego. A Parallel Hybrid Heuristic for the TSP. Applications of Evolutionary Computing, Lecture Notes in Computer Science 2037, pp 193-201, Springer, Milan (Italy), April, 2001. (ISSN: 0302-9743).

81.             Saenz, F.; Ibarra, A.; Lanchares, J.; Hidalgo, J.I.; , "Pipelined genetic architecture with fitness on the fly," Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on pp.382-385, 2001 doi:  10.1109/DSD.2001.952340.

82.             Hidalgo, J.I.; Baraglia, R.; Perego, R.; Lanchares, J.; Tirado, F. "A parallel compact genetic algorithm for multi-FPGA partitioning ," Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on , vol., no., pp.113-120, 2001
doi: 10.1109/EMPDP.2001.905033.

2000

83.             J.I. Hidalgo, J. Lanchares, R. Hermida. Partitioning and Placement for Multi-FPGA systems using Genetic algorithms.  Proceedings of the 26th EUROMICRO conference, Maastrich, (The Netherlands), 5-7 September  2000. IEEE Press. Pages 204-211 (ISBN 0-7695-0780-8)

84.             J.I. Hidalgo.  Evolutionary Algorithms for Solving the Partitioning and Placement Problems in Multi-FPGA systems. Proceedings of the 2000 Genetic and Evolutionary Computation Conference Workshop Program, Las Vegas(USA), 2000. Pp 281-284.

85.             B. de Andrés, S. Esteban, D. Rivera,  J.I. Hidalgo, M. Prieto, J. Lanchares, F. Tirado, Parallel Genetic Algorithms an application for Model Parameter Identification in Process Control, Proceedings of the 2000 Genetic and Evolutionary Computation Conference Late Breaking Papers, Las Vegas(USA), 2000. pp 65-69.

1999

86.             J.I. Hidalgo, M. Prieto, J. Lanchares, F. Tirado, B. de Andrés, S. Esteban, D. Rivera . A Method for Model Parameter Identification using Parallel Genetic Algorithms. Recent Advances in Parallel Virtual Machine and Message Passing Interface, Lecture Notes in Computer Science 1697. Springer, Barcelona (Spain). September 1999, pp 291-298. (ISSN: 0302-9743).

87.              J.I. Hidalgo, J. Lanchares, R. Hermida. Graph Partitioning methods for Multi-FPGA systems and Reconfigurable Hardware based on Genetic algorithms. Proceedings of the 1999 Genetic and Evolutionary Computation Conference Workshop Program, Orlando (USA), 1999, 357-358.

1998

88.             J.I. Hidalgo, M. Prieto, J. Lanchares, F. Tirado. A Parallel Genetic Algorithm for solving the Partitioning Problem in Multi-FPGA systems. Proceedings of 3rd international Meeting on vector and parallel processing, pp 717-722. Porto (Portugal), 21-23 June 1998.

1997

89.             J.I. Hidalgo, J. Lanchares.  Functional Partitioning for Hardware Software Codesign using Genetic Algorithm. Proceedings of the 23rd EUROMICRO conference. Budapest (Hungary), 1-4 September de 1997. IEEE Press, pp 631-638 (ISBN 0-8186-8129-2)

NATIONAL JOURNALS

90.             N. Joglar, D. Martín, A. Cuesta, M.A. Abánades y J.I. Hidalgo. "Ejercicios Adicionales Calificados en Ingeniería Técnica en Informática de Sistemas: una experiencia educativa hacia la evaluación continua". Enlaces Number 8. Jan 2008. ISSN: 1695-8543. Ed. CES-Felipe II. Available at www.cesfelipesegundo.com/revista/

91.             G. Miñana, J.I. Hidalgo, O. Garnica, J. Lanchares, J.M. Colmenar. Métricas, Metodologías y Herramientas de Simulación para Evaluar Mejoras en Arquitecturas de Bajo Consumo. Enlaces Number 3. June 2005. ISSN: 1695-8543. Ed. CES-Felipe II. Available at www.cesfelipesegundo.com/revista/

92.             J.I. Hidalgo, C. Cervigón. Una breve revisión de los algoritmos genéticos y sus aplicaciones. Enlaces Number 2 December 2005. ISSN: 1695-8543. Ed. CES-Felipe II. Available at www.cesfelipesegundo.com/revista/

NATIONAL CONFERENCES

93.             MAEB 2010 josele

94.             MAEB 2010 david

95.             Jornadas 2010

96.             Jornadas 2009 María José

97.             MAEB 2009

98.             J. Díaz, D. Lombraña, O. Garnica, F. Fernández, J.I. Hidalgo, J. Lanchares. Grid de Sobremesa + Virtualización: un modelo estándar para la obtención de recursos distribuidos. Jornadas de Paralelismo 2008. (Spain). September 2008. In press.

99.             J.I. Hidalgo, David Atienza, Sergio Belmar, Carlos M. González, Pablo Virseda, Juan Lanchares, Francisco Fernández,"Un Algoritmo Genético Multi-Objetivo para la Optimización de Memoria Dinámica en Sistemas Empotrados", Proc. of V Congreso Español sobre Metaheurísticas, Algoritmos Evolutivos y Bioinspirados (MAEB 2007), Tenerife, Spain, February 2007

100.         C. Córdoba, J.C Pedraz, C. Tenllado, J.I. Hidalgo. Hardware Gráfico Configurable: Una plataforma eficiente para la implementación de Algoritmos Evolutivos. IV Congreso Español sobre Metaheurísticas, Algoritmos Evolutivos y Bioinspirados. Actas del Primer Congreso Español de Informática (CEDI 2005). Granada (Spain). September 2005.

101.         J.I. Hidalgo, F. Fernández. Distribución equilibrada del esfuerzo de cómputo en Algoritmos Genéticos. IV Congreso Español sobre Metaheurísticas, Algoritmos Evolutivos y Bioinspirados. Actas del Primer Congreso Español de Informática (CEDI 2005). Granada (Spain). September 2005.

102.         G. Miñana, O. Garnica, J.I. Hidalgo, J. Lanchares, J.M. Colmenar. Adaptación de un simulador de potencia para UFs en procesadores de alto rendimiento. Jornadas de Paralelismo. Actas del Primer Congreso Español de Informática. (CEDI 2005). Granada (Spain). September 2005.

103.         J.M. Colmenar, O. Garnica, J.I. Hidalgo, J. Lanchares. Técnica de Estimación del Rendimiento en Pipelines Asíncronos. Actas de las XIV Jornadas de Paralelismo. ISBN: 84-89315-34-5. Universidad Carlos III de Madrid (Spain). September 2003

104.         A. Ibarra, J. Lanchares, J.M. Mendías, J.I. Hidalgo, R. Hermida. Transformación de especificaciones ecuacionales mediante Estrategias Evolutivas. 1er Congreso Español de Algoritmos Evolutivos y Bioinspirados. Mérida  (Spain). February  2002.

105.         J.I. Hidalgo, F. Fernández, J. Lanchares, J.M. Sánchez. Diseño de Sistemas Multi-FPGA mediante Algoritmos Genéticos y Programación Genética. Seminario Anual de Automática, Electrónica Industrial e Instrumentación SAAEI 2002. Alcalá de Henares (Spain)

106.         F. Fernández, J.I. Hidalgo, J. Lanchares, J.M. Sánchez, R. Hermida, M. Tomassini. Síntesis de Sistemas Multi-FPGA mediante Computación Evolutiva. 1er Congreso Español de Algoritmos Evolutivos y Bioinspirados. (Spain). February  2002.

107.          J.I. Hidalgo, J. Lanchares, R. Hermida, A.Ibarra. Un método de ubicación y evaluación de pines para Sistemas Multi-FPGA. Jornadas sobre Computación Reconfigurable y Aplicaciones. Alicante. (Spain). September 2001.

108.          J. M. Colmenar, J.I. Hidalgo J. Lanchares,. Estimación de la ocupación lógica en FPGAs para hardware reconfigurable .Jornadas sobre Computación Reconfigurable y Aplicaciones. Alicante. (Spain). September 2001.

109.          J.I. Hidalgo, J. Lanchares, R. Hermida, F. Tirado. Un Algoritmo genético compacto paralelo para la resolución de problemas de partición y ubicación en sistemas Multi-FPGA. Actas de las XI Jornadas de Paralelismo. Granada (Spain). September 2000.

110.          J.I. Hidalgo, M. Prieto, J. Lanchares, R. Hermida.  Un Algoritmo genético para la resolución del problema de la partición en sistemas Multi-FPGA. Actas de las IX Jornadas de Paralelismo. pp 349-355. San Sebastián (Spain). September 1998.

INFORMES TÉCNICOS INTERNACIONALES

111.         R. Baraglia, Raffaele Perego and J.I. Hidalgo.  An Hybrid approach for the TSP combining genetics and the Lin-Kernighan local search. Technical Report #7/2000. Istituto CNUCE, Consiglio Nazionale delle Richerche. Pisa (Italy). 2nd May 2000.

112.         R.Baraglia, Raffaele Perego and J.I. Hidalgo. Studio di algoritmi genetici compatti per la risoluzione del TSP, Technical Report B4-2000-008. Istituto CNUCE, Consiglio Nazionale delle Richerche. Pisa (Italy). (In Italian)

INFORMES TÉCNICOS NACIONALES

113.         J.I. Hidalgo, J. Millán Belsué, C. Roa Romero, J. Lanchares Dávila, (2005) KNIFE: A low-cost Reconfigurable system. E-prints complutense nº 5889.

114.         SAMOS e-prints

115.         J.I. Hidalgo,  J. Lanchares, C.J. Fernández. Partición Hardware - Software mediante algoritmos genéticos. Internal Report DACYA #001-97. Computer Architecture and System Engineering Department. Complutense University of Madrid. 30th April 1997.

116.         J.I. Hidalgo,  J. Lanchares. Resolución del Problema de la Partición mediante algoritmos genéticos. Internal Report DACYA #011-97. Computer Architecture and System Engineering Department. Complutense University of Madrid. 10th October 1997.

117.         J.I. Hidalgo,  J. Lanchares. El formato XNF (Xilinx Netlist Format). Internal Report  DACYA #004-98. Computer Architecture and System Engineering Department. Complutense University of Madrid. 22th September 1998.

118.         J.I. Hidalgo,  J. Lanchares. A new graph partitioning method for Multi-FPGA systems preserving the structure of the circuit.  Internal Report  DACYA #0013-99. Computer Architecture and System Engineering Department. Complutense University of Madrid. 16th November 1999.

119.         J. Lanchares, J.I. Hidalgo.  El algoritmo de redes evolutivas. Internal Report  DACYA #0014-99. Computer Architecture and System Engineering Department. Complutense University of Madrid. 18th November 1999.

120.         J. Lanchares, J.I. Hidalgo.  Sistemas Multi-FPGA. Internal Report DACYA #0015-99. Computer Architecture and System Engineering Department. Complutense University of Madrid. 18th November 1999.

121.         J. Lanchares, J.I. Hidalgo.  Introducción al Hardware Reconfigurable Dinámicamente.  Internal Report DACYA #0016-99. Computer Architecture and System Engineering Department. Complutense University of Madrid. 18th November 1999.

122.         J.I. Hidalgo,  J. Lanchares, R. Hermida.  Una técnica de partición y ubicación para sistemas Multi-FPGA basada en algoritmos genéticos. Informe técnico DACYA #004-2000. Computer Architecture and System Engineering Department. Complutense University of Madrid. 15th February 2000.

123.         J.I. Hidalgo, R. Baraglia and Raffaele Perego . An Hybrid approach for the TSP combining genetics and the Lin-Kernighan local search. Internal Report DACYA #008-2000. Computer Architecture and System Engineering Department. Complutense University of Madrid. 28th April 2000.

124.         J.I. Hidalgo, J. Lanchares, A. Ibarra.  Introducción a los Algoritmos Evolutivos. Internal Report DACYA #06-01. Computer Architecture and System Engineering Department. Complutense University of Madrid. 1st February 2001.

125.         J.I. Hidalgo. Recomendaciones Curriculares del IEEE/ACM para los estudios de informática (CC 2001). Internal Report DACYA #04-02. Computer Architecture and System Engineering Department. Complutense University of Madrid. 18th July 2002.

INFORMES ACADÉMICOS NACIONALES

126.         J. Lanchares, O. Garnica, J.I. Hidalgo. Diseño de circuitos integrados. Internal Report DACYA #17-99. Computer Architecture and System Engineering Department. Complutense University of Madrid. 18th November 1999.

127.         J.I. Hidalgo. Introducción a Pspice. Colegio Universitario de Segovia. 1997

128.         J.I. Hidalgo . Cuaderno de Prácticas con Pspice. Colegio Universitario de Segovia. Internal Report DACYA #03-00. Computer Architecture and System Engineering Department. Complutense University of Madrid. 15th February 2000.