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• R. Moreno, R. Hermida, M. Fernández, Register Estimation in Unscheduled Data Flow Graphs, ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 3, Jul. 1996, pp. 396-403.
• R. Moreno, R. Hermida, M. Fernández, H. Mecha, An Unified Approach for Scheduling and Allocation, Integration, The VLSI Journal, Vol. 22, 1997, pp. 1-35.
• J.M. Mendías and R. Hermida, Automatic Formal Derivation Applied to High-Level Synthesis, in "Advanced Techniques for Embedded Systems Design And Test", Kluwer Academic Pub., 1998, pp. 103-123.
• R. Maestre, F. Kurdahi, H. Sing, N. Bagherzadeh, R. Hermida, M. Fernández, Kernel Scheduling in Reconfigurable Computing, Proc. of Design Automation and Test in Europe (DATE'99), Munich, Germany, 1999, pp. 90-96
• R. Maestre, M. Fernandez, R. Hermida, N. Bagherzadeh, A Framework for Scheduling and Context Allocation in Reconfigurable Computing, 12th ACM/IEEE International Symposium on System Synthesis, (ISSS'99), San Jose, CA, USA, 1999, pp. 134-140.
• J. de Vicente, J. Lanchares, R. Hermida, Placement Optimization Based on Global-Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies, International. Workshop on Field Programmable Logic and Applications (FPL'99), Glasgow, UK, Springer Verlag, Lecture Notes in Computer Science 1673, 1999, pp. 91-100.
• O. Peñalba, J.M. Mendias, R. Hermida, A Unified Algorithm for Mutual Exclusiveness Identification, Proc. of 25th EUROMICRO Conference (EUROMICRO'99), Milan, Italy, 1999, pp. 504-510.
• J. de Vicente, J. Lanchares, R. Hermida, Adaptive FPGA Placement by Natural Optimisation, 11th IEEE Intl. Workshop on Rapid System Prototyping, Paris, France, 2000, pp. 188-193
• O. Garnica, J. Lanchares, R. Hermida, Fine-Grain Asynchronous Circuits for Low-Power High-Performance DSP Implementations, IEEE Workshop on Signal Processing Systems, Lafayette, Louisiana, USA, 2000, pp. 519-528.
• R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures, IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD'00), Austin, TX, USA, 2000, pp. 575-576.
• R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A Formal Approach to Context Scheduling for Multi-Context Reconfigurable Architectures, IEEE Transactions on VLSI Systems, Special Issue on Reconfigurable and Adaptive VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173-185.
• R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, Kernel Scheduling Techniques for Efficient Solution Space Exploration in Reconfigurable Computing, Journal of Systems Architecture (special issue on Modern Methods and Tools in Digital System Design), Vol. 47 (2001), pp. 277-292.
• M. Sánchez-Élez, M. Fernandez, R. Hermida, R. Maestre, F. J. Kurdahi, N. Bagherzadeh, A Data Scheduler for Multi-Context Reconfigurable Architectures, 14th ACM/IEEE International Symposium on System Synthesis, (ISSS'01), Montreal, Canada, 2001, pp. 177-182
• R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A Framework for Reconfigurable Computing: Task Scheduling and Context Management, IEEE Transactions on VLSI Systems.Vol. 9, No. 6, Dec. 2001, pp. 858-873. 
• M. Sánchez-Élez, M. Fernandez, R. Hermida, R. Maestre, F. J. Kurdahi, N. Bagherzadeh, A Complete Data Scheduler for Multi-Context Reconfigurable Architectures, Design Automation and Test in Europe (DATE'02), Paris, France, 2002, pp. 547-552.
• M.C. Molina, J.M. Mendías, R. Hermida, Multiple-Precision Circuits Allocation Independent of Data-Objects Length, Design Automation and Test in Europe (DATE'02), Paris, France, 2002, pp. 909-913.
• J. de Vicente, J. Lanchares, R. Hermida, FPGA Placement by Thermodynamic Combinatorial Optimization, Design Automation and Test in Europe (DATE'02), Paris, France, 2002, pp. 54-60.
• M. C. Molina, J.M. Mendías, R. Hermida, High-Level Synthesis of Multiple-Precision Circuits Independent of Data-Objects Length, ACM/IEEE Design Automation Conference (DAC'02), New Orleans, USA, 2002, pp. 612-615.
• O. Peñalba, J.M. Mendías , R. Hermida, A Global Approach to Improve Conditional Hardware Reuse in High-Level Synthesis, Journal of Systems Architecture , Vol. 47, 2002, pp. 959-975.
• J.M. Mendías, R. Hermida, O. Peñalba, A Study about the Efficiency of Formal High-Level Synthesis Applied to Verification, Integration, The VLSI Journal, Vol. 31, 2002, pp. 101-131.
• M. C. Molina, J.M. Mendías, R. Hermida, Bit-Level Scheduling of Heterogeneous Behavioral Specifications, ACM/IEEE Intl. Conference on Computer Aided Design (ICCAD’02), San Jose, CA, USA, 2002, pp. 602 - 608
• Sanchez-Elez, M.; Fernandez, M.; Anido, M.; Du, H.; Bagherzadeh, N.; Hermida, R, Low energy data management for different on-chip memory levels in multi-context reconfigurable architectures, Design Automation and Test in Europe (DATE'03), Munich, Germany, 2003, pp. 36- 41
• M. C. Molina, J.M. Mendías, R. Hermida, High-level allocation to minimize internal hardware wastage, Design Automation and Test in Europe (DATE'03), Munich, Germany, 2003, pp. 264- 269
• J. de Vicente, J. Lanchares, R. Hermida, Placement by Thermodynamic Simulated Annealing, Physics Letters A,  Vol. 317 (2003), pp 415-423.
• M.C. Molina, J.M. Mendías , R. Hermida, Behavioural specifications allocation to minimise bit level waste of functional units, IEE Proc.-Computers and Digital Techniques, Vol. 150, No. 5, September 2003, pp. 321-329
• M. C. Molina, R. Ruiz-Sautua, J.M. Mendías, R. Hermida, Behavioral Scheduling to Balance the Bit-Level Computational Effort, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'04), Lafayette, LA, USA, 2004, pp. 99-104.
• J. de Vicente, J. Lanchares, R. Hermida, Annealing placement by thermodynamic combinatorial optimization, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, Jul. 2004, pp. 310-332.
• F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida , N. Bagherzadeh, Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures, 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Stockholm, Sweden, 2004, pp. 30-35.

• R. Ruiz-Sautua, M.C. Molina, J.M. Mendías, R. Hermida, Arrival time aware scheduling to minimize clock cycle length, ASP-DAC 2005, pp. 1018-1021

• R. Ruiz-Sautua, M.C. Molina, J.M. Mendías, R. Hermida, Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis, Design Automation and Test in Europe (DATE'05), Munich, Germany, 2005, pp.1252 - 1257
• N. Genko, D. Atienza, G. De Micheli, J.M. Mendias, R. Hermida, F. Catthoor, A Complete Network-On-Chip Emulation Framework, Design Automation and Test in Europe (DATE'05), Munich, Germany, 2005, pp. 246-251
• R. Ruiz-Sautua, M. C. Molina, J.M. Mendías, R. Hermida, Performance-driven Read-After-Write Dependencies Softening in High-Level Synthesis, ACM/IEEE Intl. Conference on Computer Aided Design (ICCAD’05), San Jose, CA, USA, 2005, pp. 7-12

• N. Genko, D. Atienza, G. De Micheli, L. Benini, J.M. Mendias, R. Hermida, F. Catthoor, A novel approach for network on chip emulation, ISCAS (3) 2005, pp. 2365-2368

• J.B.Pérez-Ramas, D.Atienza, M. Peón, I. Magán, J. M. Mendias, R. Hermida, Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs, Parallel Computing (PARCO 2005), pp. 769-776

• M.C. Molina, R. Ruiz-Sautua, J.M. Mendías , R. Hermida, Bitwise Scheduling to Balance the Computational Cost of Behavioural Specifications, IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 25, No. 1, Jan. 2006, pp. 31-46
• R. Ruiz-Sautua, M.C. Molina, J. M. Mendías, R. Hermida: Pre-synthesis optimization of multiplications to improve circuit performance, Desgin Automation and Test in Europe (DATE 2006), Munich, Germany, pp 1306-1311
• José Luis Imaña, Román Hermida, Francisco Tirado, Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials, IEEE Transactions on VLSI Systems. 14(12): 1388-1393 (2006)
• María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Area optimization of multi-cycle operators in high-level synthesis, Design Automation and Test in Europe (DATE 2007), Nice, France, pp. 449-454
• David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
• M. Sánchez-Élez, M. Fernández, N. Bagherzadeh, R. Hermida, F. Kurdahi, R. Maestre, A Coarse-Grain Dynamically Reconfigurable System and Compilation Framework, (in "Fine- and Coarse-Grain Reconfigurable Computing", S. Vassiliadis, D. Soudris, eds.), Springer, 2007, ISBN 978-1-4020-6504-0
• F. Rivera, M. Sanchez-Elez, R. Hermida, N. Bagherzadeh, Scheduling Methodology for Conditional Execution of Kernels onto Multi-Context Reconfigurable Architectures, IET Computers & Digital Techniques , vol. 2, no. 3, pp.199-213, May 2008
• María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida: Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009)
• Marcos Sanchez-Elez, Nader Bagherzadeh, Román Hermida: A framework for low energy data management in reconfigurable multi-context architectures. Journal of Systems Architecture - Embedded Systems Design 55(2): 127-139 (2009)
• Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik: Using Speculative Functional Units in high level synthesis. DATE 2010, Dreseden (Germany), 1779-1784
• Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida: A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 350-363 (2011)
• Del Barrio, Alberto A.; Memik, Seda Ogrenci; Molina, Maria C.; Mendias, Jose M.; Hermida, Roman: Power optimization in heterogeneous datapaths  DATE 2011, Grenoble (France), 1 - 6
• Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida, A fragmentation aware High-Level Synthesis flow for low power heterogeneous datapaths, Integration, the VLSI Journal, (accepted, in press, available online 28 February 2012)
• José L. Imaña, Román Hermida, Francisco Tirado, Low Complexity Bit-Parallel Polynomial Basis Multipliers over Binary Fields for Special Irreducible Pentanomials, Integration, the VLSI Journal, (accepted, in press, available online 30 December 2011)
• Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Multispeculative Addition Applied to Datapath Synthesis, IEEE Transactions on Computer-Aided Design of Circuits and Systems, 31(12): 1817-1830 (2012)
• Alberto A. Del Barrio, Roman Hermida, Seda Ogrenci Memik, Jose M. Mendias, Maria C. Molina, Multispeculative Additive Trees in High-Level Synthesis,  DATE 2013, (accepted)