Román Hermida Correa

Dept. of Computer Architecture and System Engineering
School of Computer Science
Complutense University of Madrid

Teaching

Research Areas

(Español)

Selected Publications

Short CV

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Contact

Teaching

Computer Architecture (in Spanish)
Introduction to Computers (in Spanish)
High-Level and Architectural Synthesis (graduate course, partly in English)

Research areas

Reconfigurable computing and reconfigurable architectures
Embedded systems
High-Level and Architectural Synthesis

[Link to Research in ArTeCS-UCM Group Webpage]

Selected Publications

[Paper dowload: link to UCM-ATC Group Webpage]

R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A Formal Approach to Context Scheduling for Multi-Context Reconfigurable Architectures, IEEE Transactions on VLSI Systems, Special Issue on Reconfigurable and Adaptive VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173-185.
R. Maestre, F. J. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A Framework for Reconfigurable Computing: Task Scheduling and Context Management, IEEE Transactions on VLSI Systems.Vol. 9, No. 6, Dec. 2001, pp. 858-873.
M. C. Molina, J.M. Mendías, R. Hermida, High-Level Synthesis of Multiple-Precision Circuits Independent of Data-Objects Length, ACM/IEEE Design Automation Conference (DAC'02), New Orleans, USA, 2002, pp. 612-615.
O. Peñalba, J.M. Mendías , R. Hermida, A Global Approach to Improve Conditional Hardware Reuse in High-Level Synthesis, Journal of Systems Architecture , Vol. 47, 2002, pp. 959-975.
J.M. Mendías, R. Hermida, O. Peñalba, A Study about the Efficiency of Formal High-Level Synthesis Applied to Verification, Integration, The VLSI Journal, Vol. 31, 2002, pp. 101-131.
M. C. Molina, J.M. Mendías, R. Hermida, Bit-Level Scheduling of Heterogeneous Behavioral Specifications, ACM/IEEE Intl. Conference on Computer Aided Design (ICCAD’02), San Jose, CA, USA, 2002
J. de Vicente, J. Lanchares, R. Hermida, Placement by Thermodynamic Simulated Annealing, Physics Letters A, Vol. 317 (2003), pp 415-423.
M.C. Molina, J.M. Mendías , R. Hermida, Behavioural specifications allocation to minimise bit level waste of functional units, IEE Proc.-Computers and Digital Techniques, Vol. 150, No. 5, September 2003, pp. 321-329
M. C. Molina, R. Ruiz-Sautua, J.M. Mendías, R. Hermida, "Behavioral Scheduling to Balance the Bit-Level Computational Effort", IEEE Computer Society Annual Symposium on VLSI (ISVLSI'04), Lafayette, LA, USA, 2004, pp. 99-104.
J. de Vicente, J. Lanchares, R. Hermida, Annealing placement by thermodynamic combinatorial optimization, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, Jul. 2004, pp. 310-332.
F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida , N. Bagherzadeh Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures, 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Stockholm, Sweden, 2004, pp. 30-35.
R. Ruiz-Sautua, M.C. Molina, J.M. Mendías, R. Hermida, Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis, Design Automation and Test in Europe (DATE'05), Munich, Germany, 2005, pp.1252 - 1257
N. Genko, D. Atienza, G. De Micheli, J.M. Mendias, R. Hermida, F. Catthoor, A Complete Network-On-Chip Emulation Framework, Design Automation and Test in Europe (DATE'05), Munich, Germany, 2005, pp. 246-251
R. Ruiz-Sautua, M. C. Molina, J.M. Mendías, R. Hermida, Performance-driven Read-After-Write Dependencies Softening in High-Level Synthesis, ACM/IEEE Intl. Conference on Computer Aided Design (ICCAD’05), San Jose, CA, USA, 2005, pp. 7-12
M.C. Molina, R. Ruiz-Sautua, J.M. Mendías , R. Hermida, Bitwise Scheduling to Balance the Computational Cost of Behavioural Specifications, IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 25, No. 1, Jan. 2006, pp. 31-46
R. Ruiz-Sautua, M.C. Molina, J. M. Mendías, R. Hermida: Pre-synthesis optimization of multiplications to improve circuit performance, Desgin Automation and Test in Europe (DATE 2006), Munich, Germany, pp 1306-1311
José Luis Imaña, Román Hermida, Francisco Tirado, Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials, IEEE Transactions on VLSI Systems. 14(12): 1388-1393 (2006)
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Area optimization of multi-cycle operators in high-level synthesis, Design Automation and Test in Europe (DATE 2007), Nice, France, pp. 449-454
David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
M. Sánchez-Élez, M. Fernández, N. Bagherzadeh, R. Hermida, F. Kurdahi, R. Maestre, A Coarse-Grain Dynamically Reconfigurable System and Compilation Framework, (in "Fine- and Coarse-Grain Reconfigurable Computing", S. Vassiliadis, D. Soudris, eds.), Springer, 2007, ISBN 978-1-4020-6504-0
F. Rivera, M. Sanchez-Elez, R. Hermida, N. Bagherzadeh, Scheduling Methodology for Conditional Execution of Kernels onto Multi-Context Reconfigurable Architectures, IET Computers & Digital Techniques , vol. 2, no. 3, pp.199-213, May 2008
María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida: Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009)
Marcos Sanchez-Elez, Nader Bagherzadeh, Román Hermida: A framework for low energy data management in reconfigurable multi-context architectures. Journal of Systems Architecture - Embedded Systems Design 55(2): 127-139 (2009)
Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik: Using Speculative Functional Units in high level synthesis. DATE 2010, Dreseden (Germany), 1779-1784
Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida: A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 350-363 (2011)
Del Barrio, Alberto A.; Memik, Seda Ogrenci; Molina, Maria C.; Mendias, Jose M.; Hermida, Roman: Power optimization in heterogeneous datapaths DATE 2011, Grenoble (France), 1 - 6
Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Multispeculative Addition Applied to Datapath Synthesis, IEEE Transactions on Computer-Aided Design of Circuits and Systems, 31(12): 1817-1830 (2012)
Alberto A. Del Barrio, Roman Hermida, Seda Ogrenci Memik, Jose M. Mendias, Maria C. Molina, Multispeculative Additive Trees in High-Level Synthesis, DATE 2013, (accepted)
More publications ...

Short CV

Roman Hermida received a Ph.D. degree in Physics in 1984 from the Complutense University (CU) of Madrid. He has been a professor in the Department of Computer Architecture and System Engineering of the Complutense University since 1994. He served as vice-dean of the School of Computer Science of CU during the period 1995-97, and head of the departmental section of Computer Architecture of the same university from 1997 to 1999. During the period 1999-01 he served as the coordinator of the degree in Computer Science at the Felipe II College of Aranjuez. From July 2001 to June 2003 he served as Vice-Chancellor for New Technologies of the Complutense University. In the period 2006-2010 he was the Dean of the School of Computer Science.

Within the computer architecture group of the Complutense University, he has been actively involved in several projects in the field of design automation from high-level specifications, since 1987. He has led research in the following projects:

High-level synthesis of digital architectures (Jan. 1990 - Dec. 1992)
FIDIAS II: An integrated high-level synthesis system (Jul. 92 - Jul. 95)
New Methodologies for System Design Automation (Aug. 96 - Jul. 99)
Compilation of DSP applications for reconfigurable systems (joint project CU Madrid – U. California, Irvine, May 2000 - Nov. 2001)
New methodologies for high level design and verification (Jan. 2000 - Dec. 2002)
Hardware/software techniques for high-performance systems (Dec. 2002 - Dec. 2005)
Hw/Sw architecture for high-performance systems (Dec. 2005 - Dec. 2008)
Hardware/Software architecture for high-performance systems II (Jan. 2009 - Dec. 2013)

He served as deputy co-ordinator of an European Network of Laboratories, funded by the EU within the HCM programme to develop the project Behavioural Design Methodologies for Digital Systems, during the period Dec. 94 - Nov. 98.

Prof. Hermida has been reviewer and member of the Programme Committee of numerous international conferences and symposia. He has also served as Programme Chair of the IEEE/ACM 13th International Symposium on System Synthesis (ISSS 2000, Madrid), and General Chair of the IEEE/ACM 14th International Symposium on System Synthesis (ISSS 2001, Montreal). He received the "2002 VLSI Transactions Best Paper Award" for a work published in December 2001 in IEEE Transactions on VLSI Systems. He is Senior Member of IEEE, and belongs to the Steering Committee of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. He has also co-authored numerous publications in journals and international conferences in the field of design automation of digital systems, including: DAC, ICCAD, DATE, Euromicro DSD, IEEE Transactions on VLSI Systems, ACM Transactions on Design Automation of Electronic Systems, Integration, the VLSI Journal, Journal of Systems Architecture, Physics Letters A, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, etc. He has been a visiting professor at EPFL, Lausanne, Switzerland.

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